Partlist for IDEfile PCB Rev. C Dr. Patrick Schäfer, 08.03.2013 Qty Value Parts 2 22p NP0 5mm C2, C3 2 47p X7R 5mm C13, C14 20 100n X7R 5mm C1, C4, C7, C8, C9, C10, C11, C15, C16, C17, C18, C19, C20, C21, C22, C23, C24, C25, C26, C27 1 220n X7R/Z5U 5mm C28 1 2.2µ/16V Elcap 2.5mm C5 2 100µ/16V Elcap 5mm C6, C12 2 100R R3, R4 2 180R R8, R9 1 220R R11 1 470R R1 1 1k R12 1 3k3 R13 2 10k R7, R10 1 47k R2 2 8x 4k7 Type A RP1, RP2 1 10k Pot 2.5x5mm P1 2 1N4148 D2, D3 2 LED D1, D5 1 27C64, 27C128 or 27C256-20 IC3 1 62C64-15 or 6116-15 IC4 1 80C31-12 or -18 IC1 3 74HCT191 IC5, IC6, IC7 1 74HCT244 IC12 2 74HCT245 IC8, IC14 3 74HCT573 IC2, IC9, IC10 1 74LS14 IC17 1 74LS245 IC15 1 74LS280 IC16 1 GAL16V8 IC13 1 GAL22V10 IC11 1 MAX232A IC18 1 Quartz 11,059MHz or 18,432MHz HC-18 Q1 1 Jumperpins 1X02 J6, J7, J10, J11 1 Jumperpins 1X03 J8, J9 1 Jumperpins 1X05 J12 1 Pin header 90° 2X05 J4 1 Jumperpins 2X08 J3 1 Pin header 90° 2X13 J1 1 Jumperpins 2X20 J2 Remarks: * use sockets for all ICs, at least for IC3, IC11 and IC13, * select Q1 according to your microcontroller's speed and use the correct software version (-11 or -18), * use a microcontroller with "regular" divide-by-12 timing. High-speed microcontrollers use a different memory timing and may cause problems with the DMA circuit, * EPROM 200ns or faster for 18 MHz, 250ns or faster for 11 MHz * RP1, RP2 are optional pullups at the ProFile interface lines for improved EMC performance, * R4 is optional for LCD backlight. Adjust value to set brightness. * the board provides support for a Dallas Semiconductor DS5000 Emulator cpu. Connect a two-pole switch from RESET to Vcc (using J10) and from the -PSEN pin (between IC2 and IC3) to Gnd (e.g the pin close to IC8) to toggle between "LOAD" (SW closed) and "RUN" (SW open) mode. Both 11,059 and 18,432 MHz crystals allow firmware downloads at 19k2, IDEfile's regular communication speed. Refer to the DS5000 manual for details. Change History: Jul 2004: C29 omitted. This was intended as an EMC capacitor to filter spikes on the -PSTB line, but caused trouble with my Apple III due to increased risetime. This change should be implemented in all systems! May 2005: Power-on reset network changed from 10k/10µF to 47k/2.2µF. Some 74LS14 may not be able to completely discharge C5 -- TTL output impedance for pull-up is specified with 12k (-0,4mA) (In practice, most TTLs are stronger, therefore the old combination works in most cases, too). This change is not needed if your system is working fine. Apr 2006: typo corrected: Q1 should be 18,432 MHz, not 18,342! Aug 2011: Rev. C PCB with additional R3 (100R) in series with Strobe line (to damp line reflections caused by Apple II ProFile interface); LCD backlight option (pin 16 Gnd, Pin 15 Vcc via R4) at J3. Mar 2013: note on EPROM speed added